Bus Phase

MC

MD0/

MD1

Active

H

L

O

H

L

O

Power-Off

1

MC-out (MST) /

MC-in (SLV)

PD*-in

(SLV)

Link-Up

Idle

Link

Off

H

L

O

t1

Bus

Phase

H

L

PD*-in

(MST)

t2

t3

CLK-out

(SLV)

active

H

L

H

L

H

L

CLK

(MST)

t0

A

B

O

MD0 / MD1 -out

(MST) / MDn-in

(SLV)

L

C

H

t4

LM2502

SNLS176L – JANUARY 2004 – REVISED MAY 2013

www.ti.com

Figure 6. MPL Power Up Timing

OFF PHASE

In the OFF phase, both Master and Slave MPL transmitters are turned off with zero current flowing on the MC

and MD lines. Figure 7 shows the transition of the MPL bus into the OFF phase. If an MPL line is driven to a

logical Low (high current) when the OFF phase is entered it may temporarily pass through as a logical High (low

current) before reaching the zero line current state.

Figure 7. MPL Power Down Timing

The link may be powered down by asserting both the Master’s and Slaves’s PD* input pins (Low). This causes

the devices to immediately put the link to the OFF Phase and internally enter a low power state. To avoid loss of

data the Master’s PD* input should only be asserted after the MPL bus has been in the IDLE state for at least 20

MC clock cycles. This gives the Slave enough time to complete any write operations received from the MPL bus.

CPU INTERFACE COMPATIBILITY

The CPU Interface mode provides compatibility between a CPU Interface and a small form factor (SFF) Display

or other fixed I/O port application. Two options are allowed:

12

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