SYNC

10k

S

R

Q

Q

DEADTIME

ONE-SHOT

5V

2.5V

I = f(RT)

SYNC

LM5576

UP TO 5 TOTAL

DEVICES

LM5576

SYNC

12

LM5576, LM5576-Q1

SNVS447J – JANUARY 2007 – REVISED NOVEMBER 2014

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Product Folder Links: LM5576 LM5576-Q1

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Copyright © 2007–2014, Texas Instruments Incorporated

Device Functional Modes (continued)

Figure 12. Sync From Multiple Devices

Multiple LM5576 devices can be synchronized together simply by connecting the SYNC pins together. In this

configuration all of the devices will be synchronized to the highest frequency device. The diagram in Figure 13

illustrates the SYNC input/output features of the LM5576. The internal oscillator circuit drives the SYNC pin with

a strong pull-down / weak pull-up inverter. When the SYNC pin is pulled low either by the internal oscillator or an

external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the SYNC

pins of several LM5576 ICs are connected together, the IC with the highest internal clock frequency will pull the

connected SYNC pins low first and terminate the oscillator ramp cycles of the other ICs. The LM5576 with the

highest programmed clock frequency will serve as the master and control the switching frequency of the all the

devices with lower oscillator frequency.

Figure 13. Simplified Oscillator Block Diagram and Sync I/O Circuit

7.4.3 Error Amplifier and PWM Comparator

The internal high gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.225 V). The output of the error amplifier is

connected to the COMP pin allowing the user to provide loop compensation components, generally a type II

network, as illustrated in the Functional Block Diagram section. This network creates a pole at DC, a zero and a

noise reducing high frequency pole. The PWM comparator compares the emulated current sense signal from the

RAMP generator to the error amplifier output voltage at the COMP pin.