tCSH

1

st

clock

SCLK

8

th

clock

16

th

clock

CSb

tCSS

tCSH

tCSS

tODZ

SDO

tOZD

tOD

D7

D0

D1

SVA-30206511

Clock out

Chip Select out

Data Out

Data In

Control Logic

LMH6523

CLK

CSb

SDI

SDO

V+ (Logic High)

Recommended:

R = 300

to 2000

V+ (Logic) = 2.5V to 5V

For SDO (MISO) pin only:

VOH = V+,

VOL = (V+) - {0.012 * (R+20) + Vcesat}

Vcesat ~= 0.2V

R

20

12mA

Max

SVA-30206514

LMH6523

SNOSC88 – DECEMBER 2012

www.ti.com

Figure 53. Internal Operation of the SDO pin

R/Wb

Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation.

Reserved

Not used. Must be set to 0.

ADDR:

Address of register to be read or written.

DATA

In a write operation the value of this field will be written to the addressed register when the chip select pin is deasserted. In

a read operation this field is ignored.

Figure 54. Read Timing

Table 4. Read Timing Data Output on SDO Pin

PARAMETER

DESCRIPTION

tCSH

Chip select hold time

tCSS

Chip select setup time

tOZD

Initial output data delay

tODZ

High impedance delay

tOD

Output data delay

22

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