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FPD03784 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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FPD03784 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 12 page  Analog Electrical Characteristics (Continued) Symbol Parameter Conditions Min Typ Max Units A IHBIAS I SIN to IHBIAS Gain Factor 22.5 R CSTIME CSTIME resistance 5 12 k Ω C CSTIME CSTIME capacitance 100 150 pF I SIN Input Current Source 16 40 100 µA I REF Amplifier Reference Current 10 75 µA R DAC RDAC References (V GMA1 to V GMA6 and VGMA7 to VGMA12) each 12.0 15.0 18.0 k Ω V pperr Output Peak to Peak Error (gray levels 0 through 58) V GMA1 =VDD2 − 0.2V V GMA12 =VSS2 + 0.2V (Note 8) ±3 ±12 mV Output Peak to Peak Error (gray levels 59 through 63) ±5 ±25 mV Note 5: VDD2 = 9.5V, VHBIAS = 9.5V, RIREF = 220 kΩ,RISIN = 470 kΩ,VDD1 = 3.3V, DCLK = 65 MHz, RLOAD =5 kΩ,CLOAD = 50 pF, charge share time = 1.5 µs, all other swinging between VGMA1 (= 8.0V) and VGMA12 (= 0.5V) with a line time = 22 µs. Note 6: The following relationship must be maintained between the reference voltages: VDD2 >VGMA1 >VGMA2 >VGMA3 >VGMA4 >VGMA5 >VGMA6 >VGMA7 >V GMA8 >VGMA9 >VGMA10 >VGMA11 >VGMA12 >VSS2 Note 7: IMAX is the current delivered into a potential of 0.2V when the output is commanded to a potential of VDD2 − 0.2V or the current into the output from a potential of VDD2 − 0.2V when the output is commanded to 0.2V (VSS2 = 0V). Note 8: This parameter reflects the error in peak-to-peak output voltage for each gray-level when the output swings from the gray-level high value, VHxx, to its low value, VLxx. This parameter applies to every output on the die. The Typical value represents one standard deviation from ideal based on tester data. The Maximum value is a constraint of the test environment, not the performance of the part. Note 9: Current into device pins is defined as positive. Current out of device pins is defined as negative. AC Electrical Characteristics Digital AC Characteristics (3.3V Logic) Symbol Parameter Conditions Min Typ Max Units CLK Data Clock Frequency SINGLE = 1 (Note 10) 65.0 MHz SINGLE = 0 (Note 10) 27.5 MHz t WDCP CLK Clock Pulse Width SINGLE = 1 (Note 10) 5 ns SINGLE = 0 (Note 10) 10 ns t DSU Data Setup DX[5:0], POL, INVTxxx 4ns t DHLD Data Hold DX[5:0], POL, INVTxxx 4 ns t TWP LOAD Pulse Width 50 ns t LDENSU LOAD to First ENIO Setup (Note 11) 200 ns t ENDCSU ENIOx Input to CLK Setup 2.5 ns t WEN ENIOx Input Pulse Width 10 ns t ENPR ENIOx Output Prop Delay Load = 20pF 12 ns t LDLY Delay to LOAD Pulse 3 CLKs Digital AC Characteristics (2.5V Logic) Symbol Parameter Conditions Min Typ Max Units CLK Data Clock Frequency SINGLE = 1 (Note 10) 40.0 MHz SINGLE = 0 (Note 10) 17.5 MHz t WDCP CLK Clock Pulse Width SINGLE = 1 (Note 10) 10 ns SINGLE = 0(Note 10) 25 ns t DSU Data Setup DX[5:0], POL, INVTxxx 4ns t DHLD Data Hold DX[5:0], POL, INVTxxx 6 ns t TWP LOAD Pulse Width 50 ns t LDENSU LOAD to First ENIO Setup (Note 11) 200 ns t ENDCSU ENIOx Input to CLK Setup 4 ns www.national.com 3 |
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