4

LMT84-Q1

SNIS178 – OCTOBER 2017

www.ti.com

Product Folder Links: LMT84-Q1

Submit Documentation Feedback

Copyright © 2017, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.

(3)

When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V), the current at that pin should be limited to 5 mA.

7 Specifications

7.1 Absolute Maximum Ratings

See

(1) (2)

MIN

MAX

UNIT

Supply voltage

–0.3

6

V

Voltage at output pin

–0.3

(VDD + 0.5)

V

Output current

–7

7

mA

Input current at any pin(3)

–5

5

mA

Maximum junction temperature (TJMAX)

150

°C

Storage temperature Tstg

–65

150

°C

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

VALUE

UNIT

LMT84DCK-Q1 in SC70 package

V(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1)

±2500

V

Charged-device model (CDM), per AEC Q100-011

±1000

7.3 Recommended Operating Conditions

MIN

MAX

UNIT

Specified temperature

TMIN ≤ TA ≤ TMAX

°C

−50 ≤ TA ≤ 150

°C

Supply voltage (VDD)

1.5

5.5

V

(1)

For information on self-heating and thermal response time, see section Mounting and Thermal Conductivity.

(2)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

(3)

The junction to ambient thermal resistance (RθJA) under natural convection is obtained in a simulation on a JEDEC-standard, High-K

board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are

included in the PCB, per JESD 51-5.

(4)

Changes in output due to self-heating can be computed by multiplying the internal dissipation by the thermal resistance.

7.4 Thermal Information

(1)

THERMAL METRIC(2)

LMT84-Q1

UNIT

DCK (SOT/SC70)

5 PINS

RθJA

Junction-to-ambient thermal resistance (3)(4)

275

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

84

°C/W

RθJB

Junction-to-board thermal resistance

56

°C/W

ψJT

Junction-to-top characterization parameter

1.2

°C/W

ψJB

Junction-to-board characterization parameter

55

°C/W