LP5562 datasheet(15/52 Pages) TI2

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LP5562

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SNVS820B – APRIL 2013 – REVISED DECEMBER 2016

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7.3.3.2 Program Execution Engine Operation Modes

Operation modes are defined in register address 01h. Each engine (1, 2, 3) operation mode can be configured

separately. Mode registers are synchronized to a 32-kHz clock. Delay between consecutive I2C writes to

OP_MODE register (01h) need to be longer than 153 μs (typ).

Table 7. Operation Mode Register (OP_MODE (01h))

NAME

BIT

DESCRIPTION

ENG1_MODE

5:4

Engine 1 operation mode

00b = Disabled, reset engine 1 PC

01b = Load program to SRAM, reset engine 1 PC

10b = Run program defined by ENG1_EXEC

11b = Direct control from B PWM I2C register, reset engine 1 PC

ENG2_MODE

3:2

Engine 2 operation mode

00b = Disabled, reset engine 2 PC

01b = Load program to SRAM, reset engine 2 PC

10b = Run program defined by ENG2_EXEC

11b = Direct control from G PWM I2C register, reset engine 2 PC

ENG3_MODE

1:0

Engine 3 operation mode

00b = Disabled, reset engine 3 PC

01b = Load program to SRAM, reset engine 3 PC

10b = Run program defined by ENG3_EXEC

11b = Direct control from R PWM I2C register, reset engine 3 PC

7.3.3.2.1

Operation Modes

•

Disabled

–

Each channel can be configured to disabled mode. For the current engine mapped LED output brightness

will be 0 during this mode. Disabled mode resets respective engine’s PC.

•

Load program

–

LP5562 can store 16 commands for each engine (1, 2, 3). Each command consists of 16 bits. Because

one register has only 8 bits, one command requires two I2C register addresses. In order to reduce

program load time the LP5562 supports address auto increment. Register address is incremented after

each 8 data bits. The whole program memory can be written in one I2C write sequence. Program memory

is defined in the LP5562 register table, from address 10h to address 2Fh for engine 1, from address 30h

to address 4Fh for engine 2, and from address 50h to address 6Fh for engine 3. In order to access

program memory at least one channel operation mode needs to be load program.

–

SRAM memory writes are allowed only to the channel in load program mode. All engines are in hold while

one or several engines are in load program mode, and PWM values are frozen for the engines which are

not in load programmode. Program execution continues when all engines are out of load program mode.

Load program mode resets respective engine’s Program Counter (PC).

•

Run program

–

Run program mode executes the commands defined in program memory for respective engine (1, 2, 3).

Execution register bits in ENABLE register (00h) define how the program is executed. The program start

position can be programmed to Program Counter register (see Table 8). By manually selecting the PC

start value, user can write different lighting sequences to the SRAM memory, and select appropriate

sequence with the PC register. If program counter runs to end (15), next command will be executed from

program location 0. If internal clock is used in the run program mode, operation mode needs to be written

disabled (00b) before disabling the chip (with CHIP_EN bit or EN pin) to ensure that the sequence starts

from the correct program counter (PC) value when restarting the sequence. PC registers are synchronized

to 32 kHz clock. Delay between consecutive I2C writes to Program Counter (PC) registers (09h, 0Ah, 0Bh)

need to be longer than 153μs (typ.).

–

Execution registers are synchronized to 32kHz clock. Delay between consecutive I2C writes to ENABLE

–

Note that entering LOAD program or Direct Control Mode from RUN PROGRAM mode is not allowed.

Engine execution mode should be set to Hold, and Operation Mode to disabled, when changing operation

mode from RUN mode.

•

Direct control

–

In Direct control mode the engine PWM output is controlled by R, G and B PWM I2C registers.

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