Y

Z

0 V or VCC

1.62 kΩ

,

±1%

VY, or VZ

Figure 6-7. Driver Maximum Steady State Output Voltage

tc(n)

1/f0

0 V

0 V

Period Jitter

0 V

Peak to Peak Jitter

1/f0

PRBS INPUT

OUTPUT

VY -VZ

VY -VZ

CLOCK

INPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

VCC

VCC/2

tjit(per) = tc(n) -1/f0

tjit(pp)

0 V

VCC

VCC/2

0 V

VY -VZ

VY -VZ

Cycle to Cycle Jitter

0 V

VY - VZ

OUTPUT

tc(n)

tc(n+1)

tjit(cc) = | tc(n) - tc(n+1) |

A.

All input pulses are supplied by an Agilent 8304A Stimulus System.

B.

The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C.

Period jitter and cycle-to-cycle jitter are measured using a 100MHz 50 ±1% duty cycle clock input.

D.

Peak-to-peak jitter is measured using a 200Mbps 215 – 1PRBS input.

Figure 6-8. Driver Jitter Measurement Waveforms

SN65MLVD047A

SLLS736B – JULY 2006 – REVISED MARCH 2024

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