6 Detailed Description

6.1 Overview

Each data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the

AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections.

The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the

common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives

the bus line to a high or low logic level. Each output has its own output-enable (OE) input. The outputs are

disabled when their respective OE is high.

6.2 Functional Block Diagram

SN74HC253-Q1

SCLS519B – JULY 2003 – REVISED JANUARY 2025

www.ti.com

8

Submit Document Feedback

Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: SN74HC253-Q1