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TAS5624ADDVR Datasheet(PDF) 29 Page - Texas Instruments

Part # TAS5624ADDVR
Description  TAS5624A 150-W Stereo and 300-W Mono PurePath™ HD Digital Input Class-D Power Stage
PDF  42 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TAS5624ADDVR Datasheet(HTML) 29 Page - Texas Instruments

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TAS5624A
www.ti.com
SLAS844A – MAY 2012 – REVISED JANUARY 2016
Layout Guidelines (continued)
above mounting areas that contact the PCB surface. It must be supported mechanically at each end of the IC.
This mounting ensures the correct pressure to provide good mechanical, thermal and electrical contact with
TAS5624A PowerPAD. The PowerPAD contact area must be bare and must be interfaced to the PowerPAD
with a thin layer (about 1 mill) of a thermal compound with high thermal conductivity.
12.1.4.2 Printed-Circuit-Board Requirements
PCB layout, audio performance, EMC, and reliability are linked closely together, and solid grounding improves
results in all these areas. The circuit produces high, fast-switching currents, and take care controlling current flow
and minimizing voltage spikes and ground bounce at IC ground pins. Critical components must be placed for
best performance and PCB traces must be sized for the high audio currents that the IC circuit produces.
Grounding: ground planes must be used to provide the lowest impedance and inductance for power and audio
signal currents between the IC and its decoupling capacitors, LC filters and power supply connection. The area
directly under the IC must be treated as central ground area for the device, and all IC grounds must be
connected directly to that area. A matrix of vias must be used to connect that area to the ground plane. Ground
planes can be interrupted by radial traces (traces pointing away from the IC), but they must never be interrupted
by circular traces, which disconnect copper outside the circular trace from copper between it and the IC. Top and
bottom areas that do not contain any power or signal traces must be flooded and connected with vias to the
ground plane.
Decoupling capacitors: high-frequency decoupling capacitors must be located within 2 mm of the IC and
connected directly to PVDD and GND pins with solid traces. Vias must not be used to complete these
connections, but several vias must be used at each capacitor location to connect top ground directly to the
ground plane. Placement of bulk decoupling capacitors is less critical, but they still must be placed as close as
possible to the IC with strong ground return paths. Typically the heat sink sets the distance.
LC filters: LC filters must be placed as close as possible to the IC after the decoupling capacitors. The capacitors
must have strong ground returns to the IC through top and bottom grounds for effective operation.
PCB copper must be at least 1-oz. thickness. PVDD and output traces must be wide enough to carry expected
average currents without excessive temperature rise. PWM input traces must be kept short and close together on
the input side of the IC and must be shielded with ground flood to avoid interference from high power switching
signals.
The heat sink must be grounded well to the PCB near the IC, and a thin layer of highly conductive thermal
compound (about 1 mill) must be used to connect the heat sink to the PowerPAD.
Copyright © 2012–2016, Texas Instruments Incorporated
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