TAS5624A

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SLAS844A – MAY 2012 – REVISED JANUARY 2016

7.4 Thermal Information

TAS5624A

THERMAL METRIC(1)

DDV (HTSSOP)

UNIT

44 PINS

RθJA

Junction-to-ambient thermal resistance

1.9

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

0.6

°C/W

RθJB

Junction-to-board thermal resistance

1.7

°C/W

ψJT

Junction-to-top characterization parameter

0.6

°C/W

ψJB

Junction-to-board characterization parameter

1.7

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

—

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC (case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator, only used as a reference

DVDD

VDD = 12 V

3

3.3

3.6

V

node

Voltage regulator, only used as a reference

AVDD

VDD = 12 V

7.8

V

node

Operating, 50% duty cycle

20

IVDD

VDD supply current

mA

Idle, reset mode

20

50% duty cycle

12

IGVDD_X

Gate-supply current per full-bridge

mA

Reset mode

3

50% duty cycle without load

15

IPVDD_X

Full-bridge idle current

RESET low

1.9

mA

VDD and GVDD_X at 0 V

0.4

OUTPUT-STAGE MOSFETs

RDS(on), LS

Drain-to-source resistance, low-side (LS)

40

m

Ω

TJ = 25°C, excludes metallization resistance,

GVDD = 12 V

RDS(on), HS

Drain-to-source resistance, high-side (HS)

40

m

Ω

I/O PROTECTION

Vuvp,GVDD

Undervoltage protection limit, GVDD_X

8.5

V

Vuvp,GVDD, hyst

(1)

Undervoltage protection limit, GVDD_X

0.7

V

Vuvp,VDD

Undervoltage protection limit, VDD

8.5

V

Vuvp,VDD, hyst

(1)

Undervoltage protection limit, VDD

0.7

V

Vuvp,PVDD

Undervoltage protection limit, PVDD_X

8.5

V

Vuvp,PVDD,hyst

(1)

Undervoltage protection limit, PVDD_X

0.7

V

OTW(1)

Overtemperature warning

115

125

135

°C

Temperature drop needed below OTW

OTWhyst

(1)

temperature for OTW to be inactive after

25

°C

OTW event.

OTE(1)

Overtemperature error

145

155

165

°C

OTE-OTWdifferential

(1)

OTE-OTW differential

30

°C

A device reset is needed to clear FAULT

OTEHYST

(1)

25

°C

after an OTE event

OLPC

Overload protection counter

fPWM = 384 kHz

2.6

ms

Resistor-programmable, nominal peak current in

IOC

Overcurrent limit protection

15

A

1-

Ω load, ROC = 24 kΩ

Resistor-programmable, nominal peak current in

IOC_LATCHED

Overcurrent limit protection, latched

15

A

1-

Ω load, ROC = 62 kΩ

Time from application of short condition to Hi-Z of

IOCT

Overcurrent response time

150

ns

affected half-bridge

Internal pulldown resistor at output of each

Connected when RESET is active to provide

IPD

3

mA

half-bridge

bootstrap charge. Not used in SE mode.

(1)

Specified by design.

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