Rev. C 12/22

13

SIC1181KQ / SIC1182KQ

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Figure 10. Thermal Derating Curve Showing Dependence of Limited Dissipated Power P

S on Case Temperature TC

(DIN V VDE 0884-11).

Operation is allowed until reaching T

A and/or case temperature of 125 °C. Thermal stress beyond those values but below thermal derating

curve may lead to permanent functional product damage. Operating beyond thermal SOP derating curve may affect product reliability.

NOTES:

1. V

VCC = 5 V, VTOT = 25 V. RG = 5.6 Ω, no CG. The VGXX pin is connected to the G pin through a 10 nF capacitor.

Typical values are defined at T

J = 25 °C, fS = 150 kHz, duty cycle = 50%. Positive currents are assumed to be flowing into pins.

2. Pulse width ≤ 10 µs, duty cycle ≤ 1%. The maximum value is controlled by the ASIC to a safe level. The internal peak power is safely con-

trolled for R

G ≥ 0 Ω and power semiconductor module input gate capacitance CIES ≤ 47 nF. The gate sourcing peak current was determined

by the time required to charge a gate capacitance of 388 nF with R

GH = 0 (and RGL = 4 Ω) from a voltage level of 2.5 V to a voltage level of

12.5 V. The gate sinking peak current was determined by the time required to discharge a gate capacitance of 388 nF with R

GL = 0

(and R

GH = 4 Ω) from a voltage level of 22.5 V to a voltage level of 12.5 V.

3. V

IN potential changes from 0 V to 5 V within 10 ns. Delay is measured from 50% voltage increase on IN pin to 10% voltage increase on G pin.

4. V

IN potential changes from 5 V to 0 V within 10 ns. Delay is measured from 50% voltage decrease on IN pin to 10% voltage decrease on G pin.

5. Measured from 10% to 90% of V

GE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.

6. Measured from 90% to 10% of V

GE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.

7. The amount of time after primary and secondary-side supply voltages (V

VCC and VTOT) reach minimal required level for driver proper

operation. No signal is transferred from primary to secondary-side during that time.

8. Guaranteed by design.

9. Positive current is flowing out of the pin.

10. Safety distances are application dependent and the creepage and clearance requirements should follow specific equipment isolation

standards of an application. Board design should ensure that the soldering pads of an IC maintain required safety relevant distances.

11. Measured accordingly to IEC 61000-4-8 (f

S = 50 Hz, and 60 Hz) and IEC 61000-4-9.

12. All pins on each side of the barrier tied together creating a two-terminal device.

13. The amount of time needed to transfer fault event (UVLO or SNS fault) from secondary-side to SO pin.

0

20

40

60

80

100

120

140

160

TC (°C)

2.0

1.8

1.4

1.6

1.2

0.6

0.8

1.0

0.4

0.0

0.2