TPS54550PWPR datasheet(22/33 Pages) TI2

22 / 33 page

www.ti.com

BIAS AND BOOTSTRAP CAPACITORS

INT +

10–0.9

(24)

C6 +

2pR1ƒINT

(25)

LOW-SIDE FET

R3 +

pC6ƒLC

(26)

C8 +

2pR1ƒLC

(27)

ESR +

2pRESRCOUT

(28)

R5 +

2pC8 ƒESR

(29)

C7 +

8pR3ƒCO

(30)

TPS54550

SLVS623A–MARCH 2006–REVISED APRIL 2006

The measured overall loop response for the circuit is

Note that capacitors are only available in a limited

given in Figure 5. Note that the actual closed loop

range of standard values, so the nearest standard

crossover frequency is higher than intended at about

value has been chosen for each capacitor. The

25 kHz. This is primarily due to variation in the actual

measured closed loop response for this design is

values of the output filter components and tolerance

shown in Figure 30.

variation of the internal feedforward gain circuitry.

Overall the design has greater than 60 degrees of

phase margin and will be completely stable over all

Every

TPS54550

design

requires

bootstrap

combiations of line and load variability.

capacitor, C3 and a bias capacitor, C4.

The

bootstrap capacitor must be 0.1

μF. The bootstrap

Since R1 is given as 10 k

Ω and the crossover

capacitor is located between the PH pins and BOOT

frequency is selected as 13 kHz, the desired fINT can

pin. In addition, a 24-

Ω resistor is placed in series

be calculated with Equation 24:

with the bootstrap capacitor. This resistor is used to

slow down the leading edge of the high-side FET

turn on waveform. Using this resistor will dramatically

decrease the amplitude of the overshoot on the

And the value for C6 is given by Equation 25:

swtching node. The bias capacitor is connected

between the VBIAS pin and AGND. The value

should be 1.0

μF. Both capacitors should be

high-quality ceramic types with X7R or X5R grade

The first zero, fZ1, is located at 1/2 the output filter LC

dielectric for temperature stability. They should be

corner frequency, so R3 can be calculated from

placed as close to the device connection pins as

Equation 26:

possible.

The TPS54550 is designed to operate using an

The second zero, fZ2, is located at the output filter LC

external low-side FET, and the LSG pin provides the

corner frequency, so C8 can be calculated from

gate drive output. Connect the drain to the PH pin,

Equation 27:

the source to PGND, and the gate to LSG. The

TPS54550

gate

drive

circuitry

designed

accommodate most common n-channel FETs that

are suitable for this application. The SWIFT Designer

The first pole, fP1, is located to coincide with the

Software can be used to calculate all the design

output filter ESR zero frequency. This frequency is

parameters for low-side FET selection. There are

given by Equation 28:

some simplified guidelines that can be applied that

produce an acceptable solution in most designs.

The selected FET must meet the absolute maximum

ratings for the application:

where RESR is the equivalent series resistance of the

output capacitor.

Drain-source voltage (VDS) must be higher than the

maximum voltage at the PH pin, which is VINMAX +

In this case, the ESR zero frequency is 35.4 kHz,

0.5 V.

and R5 can be calculated from Equation 29:

Gate-source voltage (VGS) must be greater than 8 V.

Drain current (ID) must be greater than 1.1 x IOUTMAX.

The final pole is placed at a frequency above the

Drain-source on resistance (rDSON) should be as

closed loop crossover frequency high enough to not

small as possible, less than 30 m

Ω is desirable.

cause the phase to decrease too much at the

Lower values for rDSON result in designs with higher

crossover frequency while still providing enough

efficiencies. It is important to note that the low-side

attenuation so that there is little or no gain at the

FET on time is typically longer than the high-side

switching frequency. The fP2 pole location for this

FET on time, so attention paid to low-side FET

circuit is set to 4 times the closed loop crossover

parameters can make a marked improvement in

frequency. The last compensation component value

overall efficiency.

C7 can be derived from Equation 30:

Total gate charge (Qg) must be less than 50 nC.

Again, lower Qg characteristics result in higher

efficiencies.

Submit Documentation Feedback

TPS54550PWPR Datasheet(PDF) 22 Page - Texas Instruments

TPS54550PWPR Datasheet(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL