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Reading Data

RESET

ADS8411

SLAS369B – APRIL 2002 – REVISED DECEMBER 2004

PRINCIPLES OF OPERATION (continued)

The ADS8411 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active

when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST.

This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be

attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used

for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher

byte of the bus. Refer to Table 1 for ideal output codes.

Table 1. Ideal Input Voltages and Output Codes

DESCRIPTION

ANALOG VALUE

DIGITAL OUTPUT

Full scale range

Vref

STRAIGHT BINARY

Least significant bit (LSB)

Vref/65536

BINARY CODE

HEX CODE

Full scale

Vref– 1 LSB

1111 1111 1111 1111

FFFF

Midscale

Vref/2

1000 0000 0000 0000

8000

Midscale – 1 LSB

Vref/2 – 1 LSB

0111 1111 1111 1111

7FFF

Zero

0 V

0000 0000 0000 0000

0000

The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB-LSB) if BYTE is low.

The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this

case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on

pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8.

These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.

Table 2. Conversion Data Readout

DATA READ OUT

BYTE

DB15–DB8 Pins

DB7-DB0 Pins

High

D7–D0

All one's

Low

D15–D8

D7-D0

RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time

is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In

addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation

mode no later than 20 ns after RESET input is brought high.

The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except

for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling

edge of CS, whichever is later.

Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when

the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific

converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an

internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does

not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following

steps.

•

Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy

the timing as specified by the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure

a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated

RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.

•

Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by

the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure a reset.The falling edge of

CS causes a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the

falling edge is replaced by the falling edge of CS.

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