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POWER-ON INITIALIZATION

LAYOUT

ADS8411

SLAS369B – APRIL 2002 – REVISED DECEMBER 2004

RESET is not required after power on. An internal power-on-reset circuit generates the reset. To ensure that all

of the registers are cleared, the three conversion cycles must be given to the converter after power on.

For optimum performance, care should be taken with the physical layout of the ADS8411 circuitry.

As the ADS8411 offers single-supply operation, it is often used in close proximity with digital logic,

microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and

the higher the switching speed, the more difficult it is to achieve good performance from the converter.

The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground

connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving

any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient

voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby

digital logic, or high power devices.

The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the

external event.

On average, the ADS8411 draws very little current from an external reference, as the reference voltage is

internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive

the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a 1-µF storage capacitor

are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the

same ground plane under the device.

The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the

analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal

processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal

layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.

As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate

from the connection for digital logic until they are connected at the power entry point. Power to the ADS8411

should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device

as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is

recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor

or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply,

removing the high frequency noise.

Table 3. Power Supply Decoupling Capacitor Placement

POWER SUPPLY PLANE

CONVERTER ANALOG SIDE

CONVERTER DIGITAL SIDE

SUPPLY PINS

(4,5), (8,9), (10,11), (13,15),

Pin pairs that require shortest path to decoupling capacitors

(24,25), (34, 35)

(43,44), (45,46)

Pins that require no decoupling

12, 14

37

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