LM89 datasheet(16/40 Pages) TI2

16 / 40 page

SMBCLK

SMBDat

Ack

LM89

Start

Master

Address byte.

No Ack

Master

Stop

Master

Frame 1

Serial Bus Address Byte

Frame 2

Data Byte from the LM89

R/W

LM89

SNIS128D – AUGUST 2002 – REVISED JUNE 2014

www.ti.com

9.3.8.1 SMBus Timing Diagrams

Figure 9. LM89 Timing Diagram

(A) Serial Bus Write To The Internal Command Register Followed By A The Data Byte

Figure 10. LM89 Timing Diagram

(B) Serial Bus Write To The Internal Command Register

Figure 11. LM89 Timing Diagram

9.3.9 Serial Interface Reset

In the event that the SMBus Master is RESET while the LM89 is transmitting on the SMBData line, the LM89

must be returned to a known state in the communication protocol. This may be done in one of two ways:

1. When SMBData is LOW, the LM89 SMBus state machine resets to the SMBus idle state if either SMBData

or SMBCLK are held low for more than 35 ms (tTIMEOUT). Note that according to SMBus specification 2.0 all

devices are to timeout when either the SMBCLK or SMBData lines are held low for 25-35 ms. Therefore, to

insure a timeout of all devices on the bus the SMBCLK or SMBData lines must be held low for at least 35

ms.

2. When SMBData is HIGH, have the master initiate an SMBus start. The LM89 will respond properly to an

Submit Documentation Feedback

Product Folder Links: LM89

LM89 Datasheet(PDF) 16 Page - Texas Instruments