TLC320AC02 datasheet(49/93 Pages) TI2

49 / 93 page

4–2

D15

D14

D13

D12

D11

tf(SCLK)

0.8 V

SCLK

FS†

tr(SCLK)

td(CH-FH)

td(CH-FL)

0.8 V

2 V

td(CH-DOUT)

D15

D14

D13

D12

D11

tsu(DIN)

th(DIN)

DOUT‡

DIN

2 V

† The time between falling edges of two primary FS signals is the conversion period.

‡ The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling

edge of the shift clock.

Figure 4 – 2. AIC Stand-Alone and Master-Mode Timing

D15

D14

D13

D12

D11

2 V

tf(SCLK)

0.8 V

SCLK

FS†

tr(SCLK)

tc(SCLK)

2 V

td(CH-DOUT)

D15

D14

D13

D12

D11

tsu(DIN)

th(DIN)

DOUT‡

DIN

† The time between falling edges of two primary FS signals is the conversion period.

‡ The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling

edge of the shift clock.

§ The high-to-low transition of FS must must occur within

±1/4 of a shift-clock period around the 2-V level of the shift clock

for the codec mode.

Figure 4 – 3. AIC Slave and Codec Emulation Mode

TLC320AC02 Datasheet(PDF) 49 Page - Texas Instruments

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