7.5 Electrical Characteristics

at TA = –40°C to +85°C (unless otherwise noted); typical values are at TA = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

VDD = 2.5 V to 6 V, IOH = –500 µA

VDD – 0.2

V

VDD = 3.3 V, IOH = –2 mA

VDD – 0.4

VDD = 6 V, IOH = –4 mA

VDD – 0.4

VOL

Low-level output voltage

VDD = 2 V to 6 V, IOH = 500 µA

0.3

V

VDD = 3.3 V, IOH = 2 mA

0.4

VDD = 6 V, IOH = 4 mA

0.4

Power-up reset voltage(1)

VDD ≥ 1.1 V, IOL = 50 µA

0.2

V

VIT–

Negative-going input

threshold voltage(2)

TLV809J25

TA = –40°C to +85°C

2.20

2.25

2.30

V

TLV809L30

2.58

2.64

2.70

TLV809K33

2.87

2.93

2.99

TLV809I50

4.45

4.55

4.65

Vhys

Hysteresis

TLV809J25

30

mV

TLV809L30

35

TLV809K33

40

TLV809I50

60

IDD

Supply current

VDD = 2 V, RESET is unconnected

9

12

µA

VDD = 6 V, RESET is unconnected

20

25

CI

Input capacitance

VI = 0 V to VDD

5

pF

(1)

The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 ms/V.

(2)

To ensure best stability of the threshold voltage, place a bypass capacitor ( 0.1-µF ceramic) near the supply pins.

7.6 Timing Requirements

at TA = 25°C, RL = 1 MΩ, and CL = 50 pF

MIN

NOM

MAX

UNIT

tw

Pulse duration at VDD

VDD = VIT– + 0.2 V, VDD = VIT– – 0.2 V

10

µs

7.7 Switching Characteristics

at TA = 25°C, RL = 1 MΩ, and CL = 50 pF

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

td

Delay time

VDD ≥ VIT– + 0.2 V; see Figure 7-1

120

200

280

ms

tPHL

Propagation (delay) time,

high-to-low-level output

VDD to RESET delay

VIL = VIT– – 0.2 V, VIH = VIT– + 0.2 V

10

µs

TLV809

SLVSA03F – JUNE 2010 – REVISED DECEMBER 2020

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