Input Amplitude (dBFS)

80

70

60

50

40

30

20

10

0

−60

−50

0

dBc

dBFS

−40

−30

−20

−10

f

IN = 5MHz

Input Amplitude (dBFS)

120

100

80

60

40

20

0

−60

−50

0

dBc

dBFS

−40

−30

−20

−10

f

IN = 5MHz

Duty Cycle (%)

76

74

72

70

68

66

64

35

40

65

f

IN = 5MHz

45

50

55

60

Duty Cycle (%)

76

74

72

70

68

66

64

35

40

65

f

IN = 5MHz

45

50

55

60

Duty Cycle (%)

95

90

85

80

75

70

65

35

40

65

f

IN = 5MHz

45

50

55

60

Sample Rate (MSPS)

80

76

72

68

64

60

20

25

65

f

IN = 5MHz

30

35

40

45

50

55

60

ADS5272

www.ti.com...................................................................................................................................................... SBAS324C – JUNE 2004 – REVISED JANUARY 2009

TYPICAL CHARACTERISTICS (continued)

TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty

cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per

channel, 16kFFT, and 8 averages, unless otherwise noted.

SWEPT POWER — SINAD

SWEPT POWER — SFDR

Figure 19.

Figure 20.

SNR vs DUTY CYCLE

SINAD vs DUTY CYCLE

Figure 21.

Figure 22.

SFDR vs DUTY CYCLE

SNR vs SAMPLE RATE

Figure 23.

Figure 24.

Copyright © 2004–2009, Texas Instruments Incorporated

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