THEORY OF OPERATION

OVERVIEW

DRIVING THE ANALOG INPUTS

CM Buffer

Internal

Voltage

Reference

Input

Circuitry

IN+

IN

−

V

CM

600

Ω

600

Ω

ADS5272

NOTE: Dashed area denotes one of eight channels.

ADS5272

SBAS324C – JUNE 2004 – REVISED JANUARY 2009...................................................................................................................................................... www.ti.com

data externally has multiple advantages, such as a

reduced number of output pins (saving routing space

on the board), reduced power consumption, and

The ADS5272 is an 8-channel, high-speed, CMOS

reduced effects of digital noise coupling to the analog

ADC.

It

consists

of

a

high-performance

circuit inside the ADS5272.

sample-and-hold circuit at the input, followed by a

The ADS5272 operates from two sets of supplies and

12-bit ADC. The 12 bits given out by each channel

grounds. The analog supply/ground set is denoted as

are serialized and sent out on a single pair of pins in

AVDD/AVSS, while the digital set is denoted by

LVDS format. All eight channels of the ADS5272

LVDD/LVSS.

operate from a single clock referred to as ADCLK.

The sampling clocks for each of the eight channels

are generated from the input clock using a carefully

matched clock buffer tree. The 12x clock required for

The analog input biasing is shown in Figure 34. The

the serializer is generated internally from ADCLK

inputs are biased internally using two 600

Ω resistors

using a phase lock loop (PLL). A 6x and a 1x clock

to enable ac-coupling. A resistor greater than 20

Ω is

are also output in LVDS format along with the data to

recommended in series with each input pin.

enable easy data capture. The ADS5272 operates

from internally generated reference voltages that are

A 4pF sampling capacitor is used to sample the

trimmed to ensure matching across multiple devices

inputs. The choice of the

external

ac-coupling

on a board. This feature eliminates the need for

capacitor is dictated by the attenuation at the lowest

external routing of reference lines and also improves

desired input frequency of operation. The attenuation

matching of the gain across devices. The nominal

resulting from using a 10nF ac-coupling capacitor is

values of REFT and REFB are 1.95V and 0.95V,

0.04%.

respectively. These values imply that a differential

input of –1V corresponds to the zero code of the

ADC, and a differential input of +1V corresponds to

the full-scale code (4095 LSB). VCM (common-mode

voltage of REFT and REFB) is also made available

externally through a pin, and is nominally 1.45V.

The ADC employs a pipelined converter architecture

consisting of a combination of multi-bit and single-bit

internal stages. Each stage feeds its data into the

digital

error

correction

logic,

ensuring

excellent

differential linearity and no missing codes at the

12-bit level. The pipeline architecture results in a data

latency of 6.5 clock cycles.

The output of the ADC goes to a serializer that

operates from a 12x clock generated by the PLL. The

12 data bits from each channel are serialized and

sent LSB first. In addition to serializing the data, the

serializer also generates a 1x clock and a 6x clock.

Figure 34. Analog Input Bias Circuitry

These clocks are generated in the same way the

serialized data is generated, so these clocks maintain

If

the

input

is

dc-coupled,

then

the

output

perfect synchronization with the data. The data and

common-mode voltage of the circuit driving the

clock outputs of the serializer are buffered externally

ADS5272 should match the VCM (which is provided as

using LVDS buffers. Using LVDS buffers to transmit

an output pin) to within ±50mV. It is recommended

that the output common-mode of the driving circuit be

derived from VCM provided by the device.

20

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