 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADS7813 Datasheet(PDF) 12 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADS7813 Datasheet(HTML) 12 Page - Texas Instruments |
|
|
12 / 27 page  ADS7813 12 SBAS043C www.ti.com External DATACLK Active After the Conversion and During the Next Conversion Figure 8 shows a method that is a hybrid of the two previous approaches. This method works very well for microcontrollers that do serial transfers 8 bits at a time and for slower microcontrollers. For example, if the fastest serial clock that the microcontroller can produce is 1 µs, the approach shown in Figure 6 would result in a diminished throughput (26kHz maximum conversion rate). The method described in Figure 7 could not be used without risk of affecting the conversion result (the clock would have to be active after time t2). The approach in Figure 8 results in an improved throughput rate (33kHz maximum with a 1 µs clock) and DATACLK is not active after time t2. COMPATIBILITY WITH THE ADS7812 The only difference between the ADS7812 and the ADS7813 is in the internal control logic and the digital interface. Since the ADS7812 is a 12-bit converter, the internal shift register is 12 bits wide. In addition, only 12-bit decisions are made during the conversion. Thus, the ADS7812’s conversion time is approximately 75% of the ADS7813’s. In the internal DATACLK mode, the ADS7812 produces 12 DATACLK periods during the conversion instead of the ADS7813’s 16 (see Figure 5). In the external DATACLK mode, the ADS7812 can accept 16 clock periods on DATACLK. At the start of the 13th clock cycle, the DATA output will go LOW and remain LOW. Thus, Figures 6, 7, 8, and the associated times in Table II can also be used for the ADS7812, but the last four bits of the conversion result will be zero. CHIP SELECT (CS) The CS input allows the digital outputs of the ADS7813 to be disabled and gates the external DATACLK signal when EXT/INT is HIGH. See Figure 9 for the enable and disable time associated with CS and Figure 3 for a block diagram of the ADS7813’s logic. The digital outputs can be disabled at any time. Note that a conversion is initiated on the falling edge of CONV even if CS is HIGH. If the EXT/INT input is LOW (internal DATACLK) and CS is HIGH during the entire conversion, the previous conversion result will be lost (the serial transmission occurs but DATA and DATACLK are disabled). TABLE IV. Complete List of Ideal Input Ranges. ANALOG CONNECT CONNECT CONNECT INPUT INPUT R1IN R2IN R3IN IMPEDANCE RANGE (V) TO TO TO (k Ω) COMMENT 0.3125 to 2.8125 VIN VIN VIN > 10,000 Specified offset and gain –0.417 to 2.916 VIN VIN BUF 26.7 VIN cannot go below GND – 0.3V 0.417 to 3.750 VIN VIN GND 26.7 Offset and gain not specified ±3.333 VIN BUF VIN 21.3 Specified offset and gain –15 to 5 VIN BUF BUF 45.7 Offset and gain not specified ±10 VIN BUF GND 45.7 Specified offset and gain 0.833 to 7.5 VIN GND VIN 21.3 Offset and gain not specified –2.5 to 17.5 VIN GND BUF 45.7 Exceeds absolute maximum VIN 2.5 to 22.5 VIN GND GND 45.7 Exceeds absolute maximum VIN 0 to 2.857 BUF VIN VIN 45.7 Offset and gain not specified –1 to 3 BUF VIN BUF 21.3 VIN cannot go below GND – 0.3V 0 to 4 BUF VIN GND 21.3 Specified offset and gain –6.25 to 3.75 BUF BUF VIN 26.7 Offset and gain not specified 0 to 10 BUF GND VIN 26.7 Specified offset and gain 0.357 to 3.214 GND VIN VIN 45.7 Offset and gain not specified –0.5 to 3.5 GND VIN BUF 21.3 VIN cannot go below GND – 0.3V 0.5 to 4.5 GND VIN GND 21.3 Specified offset and gain ±5 GND BUF VIN 26.7 Specified offset and gain 1.25 to 11.25 GND GND VIN 26.7 Offset and gain not specified Active HI-Z HI-Z BUSY, DATA, DATACLK(1) CS t 27 t 26 NOTE: (1) DATACLK is an output only when EXT/INT is LOW. FIGURE 9. Enable and Disable Timing for Digital Outputs. ANALOG INPUT The ADS7813 offers a number of input ranges. This is accomplished by connecting the three input resistors to either the analog input (VIN), to ground (GND), or to the 2.5V reference buffer output (BUF). Table I shows the input ranges that are typically used in most data acquisition applications. These ranges are all specified to meet the specifications given in the Specifications table. Table IV contains a complete list of ideal input ranges, associated input connections, and comments regarding the range. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
