AFE5808ZCF.B datasheet(22/75 Pages) TI2

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AFE5808

SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014

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TIMING CHARACTERISTICS

(1)

Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, Differential clock, CLOAD = 5

pF, RLOAD = 100 Ω, 14 Bit, sample rate = 65 MSPS, unless otherwise noted. Minimum and maximum values are across the

full temperature range TMIN = 0°C to TMAX = 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

The delay in time between the rising edge of the input sampling

Aperture delay

0.7

clock and the actual time at which the sampling occurs

Aperture delay

Across channels within the same device

±150

matching

Aperture jitter

450

Fs rms

Input

ADC latency

Default, after reset, or / 0 x 2 [12] = 1, LOW_LATENCY = 1

11/8

clock

cycles

tdelay

Data and frame clock

Input clock rising edge (zero cross) to frame clock rising edge (zero

5.4

delay

cross) minus 3/7 of the input clock period (T).

Δtdelay

Delay variation

At fixed supply and 20°C T difference. Device to device

–1

tRISE

Data rise time

Rise time measured from –100 to 100 mV Fall time measured from

0.14

100 to –100 mV 10 MHz < fCLKIN < 65MHz

tFALL

Data fall time

0.15

tFCLKRISE

Frame clock rise time

Rise time measured from –100 to 100 mV Fall time measured from

0.14

100 to –100 mV 10 MHz < fCLKIN < 65MHz

tFCLKFALL

Frame clock fall time

0.15

Frame clock duty cycle

Zero crossing of the rising edge to zero crossing of the falling edge

48%

50%

52%

tDCLKRISE

Bit clock rise time

Rise time measured from –100 to 100 mV Fall time measured from

0.13

100 to –100 mV 10 MHz < fCLKIN < 65MHz

tDCLKFALL

Bit clock fall time

0.12

Zero crossing of the rising edge to zero crossing of the falling edge

Bit clock duty cycle

46%

54%

10MHz < fCLKIN < 65MHz

(1)

Timing parameters are specified by design and characterization; not production tested.

OUTPUT INTERFACE TIMING

(1) (2) (3)

Setup Time (tsu), ns

Hold Time (th), ns

tPROG = (3/7)x T + tdelay, ns

fCLKIN,

Input Clock Zero-Cross (rising edge)

Input Clock

Data Valid to Bit Clock Zero-

Bit Clock Zero-Crossing to Data

to Frame Clock Zero-Cross (rising

Frequency

Crossing

Invalid

edge)

MHz

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

0.24

0.37

0.24

0.38

12.5

0.41

0.54

0.46

0.57

13.9

14.4

0.55

0.70

0.61

0.73

16.7

0.87

1.10

0.94

1.1

18.5

19.5

20.1

1.30

1.56

1.46

1.6

25.7

26.7

27.3

(1)

FCLK timing is the same as for the output data lines. It has the same relation to DCLK as the data pins. Setup and hold are the same

for the data and the frame clock.

(2)

Data valid is logic HIGH = +100 mV and logic LOW = –100 mV

(3)

Timing parameters are specified by design and characterization; not production tested.

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