CDCM1802

S0

S1

EN

REN = 60lQ

RS1 = 0

RS0 = open

Setting for Mode 4:

EN = VDD/2

S1 = 0

S0 = 1

12

CDCM1802

SCAS759C – APRIL 2004 – REVISED JULY 2017

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Copyright © 2004–2017, Texas Instruments Incorporated

Device Functional Modes (continued)

Figure 11. Control Pin Setting for Example

Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing

a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.

Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to

VDD/2, the installed resistor needs a value of 60 kΩ with a tolerance better or equal to 10%.

(1)

The LVPECL outputs are open emitter stages. Thus, if you leave the unused LVPECL output Y0

unconnected, then the current consumption is minimized and noise impact to remaining outputs is

neglectable. Also, each output can be individually disabled by connecting the corresponding VDD input

to GND.

Table 1. Selection Mode Table

MODE

EN

S1

S0

LVPECL(1)

LVCMOS

Y0

Y1

0

0

X

X

Off (high-z)

Off (high-z)

1

VDD/2

0

VDD/2

/1

/1

2

VDD/2

VDD/2

1

/1

/2

3

1

0

0

/1

/4

4

VDD/2

0

1

/2

/2

5

1

0

1

/2

/4

6

VDD/2

0

0

/4

/4

7

VDD/2

1

0

/4

/8

8

VDD/2

VDD/2

VDD/2

/8

/1

9

1

1

0

/8

/4

10

1

1

1

Off (high-z)

/4

8.4.2 Device Behavior During RESET and Control Pin Switching

8.4.2.1 Output Behavior When Enabling the Device (EN = 0

→ 1)

In disable mode (EN = 0), all output drivers are switched in high-Z mode. The bandgap, current references, the

amplifier, and the S0 and S1 control inputs are also switched off. In the same mode, all flip-flops will be reset.

The typical current consumption is likely below 500 µA (to be measured).

When the device will be enabled again it takes maximal 1 µs for the settling of the reference voltage and

currents. During this time the output Y0 and Y0 drive a high signal. Y1 is unknown (could be high or low). After

the settle time, the outputs go into the low state. Due to the synchronization of each output driver signal with the

input clock, the state of the waveforms after enabling the device look like those shown in Figure 12. The inverting

input and output signal is not included. The Y:/1 waveform is the undivided output driver state.