tm

May 2007

©1993 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74VHC4040 Rev. 1.3

74VHC4040

12-Stage Binary Counter

Features

■ High speed; fMAX = 210MHz at VCC = 5V

■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C

■ High noise immunity: VNIH = VNIL = 28% VCC (Min.)

■ Power down protection is provided on all inputs

■ Wide operating voltage range: VCC (Opr.) = 2V – 5.5V

■ Low noise: VOLP = 0.8V (Max.)

■ Pin and function compatible with 74HC4040

General Description

The VHC4040 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The VHC4040 is a 12-stage counter

which increments on the negative edge of the input clock

and all outputs are reset to a low level by applying a

logical high on the reset input. An input protection circuit

insures that 0V to 7V can be applied to the inputs without

regard to the supply voltage. This device can be used to

interface 5V to 3V systems and two supply systems such

as battery backup. This circuit prevents device destruc-

tion due to mismatched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number.

Connection Diagram

Pin Descriptions

Order Number

Package

Number

Package Description

74VHC4040M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC4040MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Pin Names

Description

Q0–Q11

Flip-Flop Outputs

CP

Negative Edged Triggered Clock

MR

Master Reset