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ISO5852S-Q1

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SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016

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Copyright © 2016, Texas Instruments Incorporated

9.3 Feature Description

9.3.1 Supply and Active Miller Clamp

The ISO5852S-Q1 supports both bipolar and unipolar power supply with active Miller clamp.

For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its

emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its

gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the

IGBT gate, but connecting CLAMP output of the gate driver to the IGBT gate is also not an issue. Typical values

of VCC2 and VEE2 for bipolar operation are 15-V and -8-V with respect to GND2.

For operation with unipolar supply, typically, VCC2 is connected to 15-V with respect to GND2, and VEE2 is

connected to GND2. In this use case, the IGBT can turn on due to additional charge from IGBT Miller

capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the

CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.

Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage

transitions below 2-V the CLAMP current output is activated.

9.3.2 Active Output Pulldown

The Active output pulldown feature ensures that the IGBT gate OUTH/L is clamped to VEE2 to ensure safe IGBT

off-state, when the output side is not connected to the power supply.

9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output

Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply VCC1

drops below VIT-(UVLO1), irrespective of IN+, IN– and RST input till VCC1 goes above VIT+(UVLO1).

In similar manner, the IGBT is turned-off, if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN– and

RST input till VCC2 goes above VIT+(UVLO2).

Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection

feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise,

RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for

operation.

9.3.4 Soft Turnoff, Fault (FLT) and Reset (RST)

During IGBT overcurrent condition, a mute logic initiates a soft-turn-off procedure which disables, OUTH, and

pulls OUTL to low over a time span of 2 μs. When desaturation is active, a fault signal is sent across the isolation

barrier pulling the FLT output at the input side low and blocking the isolator input. mute logic is activated through

the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a

active-low pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for at-

least the specified minimum duration (800 ns), device input logic can be enabled or disabled.

9.3.5 Short Circuit Clamp

Under short circuit events it is possible that currents are induced back into the gate-driver OUTH/L and CLAMP

pins due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes

on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly

higher than the output side supply.