Table 7-1. GVDD UVLO Logic Operation

CONDITION (VBST- SH > VBSTR)

IN

SD

GH

GL

VGVDD – GND < VGVDDR during device start-up

H

L

L

L

L

H

L

L

H

H

L

L

L

L

L

L

VGVDD – GND < VGVDDR – VDDHYS after device start-up

H

L

L

L

L

H

L

L

H

H

L

L

L

L

L

L

Table 7-2. BST UVLO Logic Operation

CONDITION (VGVDD > VGVDDR)

IN

SD

GH

GL

VBST-SH < VBSTR during device start-up

H

L

L

L

L

H

L

H

H

H

L

L

L

L

L

L

VBST-SH < VBSTR – VBSTHYS after device start-up

H

L

L

L

L

H

L

H

H

H

L

L

L

L

L

L

7.3.2 Input Stages

The SD input pin controls the outputs by turning GH and GL off when the SD pin is held low, regardless of the

IN input pin state. When SD pin is held high, the IN pin controls the state of the GL and GH outputs allowing the

device to be used in single PWM input applications. When IN pin is low, GL output will turn on and GH output will

turn off, and when IN pin is high, GL output will turn off and GH output will turn on.

The device has built-in fixed dead time with a typical value of 475 ns. A small filter at each of the inputs of the

driver further improves system robustness in noise-prone applications. Both IN and SD have internal pulldown

resistors with typical value of 200 kΩ. Thus, when the inputs are floating, the outputs are held low.

7.3.3 Level Shift

The level shift circuit is the interface from the high-side input, which is a GND referenced signal, to the high-side

driver stage, which is referenced to the switch node (SH). The level shift allows control of the GH output which is

referenced to the SH pin and provides excellent delay matching with the low-side driver.

7.3.4 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,

and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The

low-side output stage is referenced to GND and the high-side is referenced to SH.

7.3.5 SH Transient Voltages Below Ground

In most applications, the body diode of the external low-side power MOSFET clamps the SH node to ground.

In some situations, board capacitance and inductance can cause the SH node to transiently swing several volts

below ground, before the body diode of the external low-side MOSFET clamps this swing. The SH pin in the

LM2104 is allowed to swing below ground as long as specifications are not violated and conditions mentioned in

this section are followed.

SH must always be at a lower potential than GH. Pulling GH more negative than specified conditions can

activate parasitic transistors which may result in excessive current flow from the BST supply. This may result

in damage to the device. The same relationship is true with GL and GND. If necessary, a Schottky diode can

LM2104

SNVSCH8A – SEPTEMBER 2023 – REVISED OCTOBER 2023

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