LMP91051

SNAS581B – MARCH 2012 – REVISED MAY 2013

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Table 3. Write / Read Instruction Format

BIT[7]

BIT[6:4](1)

BIT[3:0]

0 : Write Instruction

Reserved to 0

Address

1 : Read Instruction

(1)

Specifying any value other than zero in Bit[6:4] is prohibited.

REGISTERS

This section describes the programmable registers and the associated programming sequence, if any, for the

device. The following table shows the summary listing of all the registers that are available to the user and their

power-up values.

POWER-UP/RESET

TITLE

ADDRESS (HEX)(1)

TYPE

VALUE (HEX)

Device

Read-Write

0x0

0x0

Configuration

(Read allowed in SDIO Mode)

DAC

Read-Write

0x1

0x80

Configuration

(Read allowed in SDIO Mode)

SDIO Mode

0xF

Write-only

0x0

Enable

(1)

Recommended values must be programmed where they are indicated in order to avoid unexpected results. Avoid writing to addresses

not mentioned in the document; this could cause unexpected results.

Device Configuration – Device Configuration Register (Address 0x0)

BIT

BIT SYMBOL

DESCRIPTION

0: IN1 (default)

7

INP_SEL

1: IN2

00: PGA1 OFF PGA2 OFF (default)

01: PGA1 OFF, PGA2 ON

[6:5]

EN

10: PGA1 ON, PGA2 OFF

11: PGA1 ON, PGA2 ON

0: PGA1 to PGA2 direct (default)

4

EXT_FILT

1: PGA1 to PGA2 via external filter

0 : 1.15V (default)

3

CMN_MODE

1 : 2.59V

00: 4 (default)

01: 8

[2:1]

GAIN2

10: 16

11: 32

0: 250 (default)

0

GAIN1

1: 42

DAC Configuration – DAC Configuration Register (Address 0x1)

The output DC level will shift according to the formula Vout_shift = –33.8mV * (NDAC – 128).

BIT

BIT SYMBOL

DESCRIPTION

[7:0]

NDAC

128 (0×80): Vout_shift = –33.8mV * (128 – 128) = 0mV (default)

SDIO Mode – SDIO Mode Enable Register (Address 0xf)

Write-only

BIT

BIT SYMBOL

DESCRIPTION

To enter SDIO Mode, write the successive sequence 0×FE and 0×ED. Write

[7:0]

SDIO_MODE_EN

anything other than this sequence to get out of mode.

16

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