MSP430

AVSS/DVSS

LMP91051

IN2

Active

Thermopile

OUT

A0

A1

VDD

CMOUT

IN1

VIO

A/D

VIO

DVCC

GND

CSB

SDIO

SCLK

GPIO

CLK

MOSI

VDD

AVCC

VDD

VIO

Reference

Thermopile

OUT

IN2

DAC

VREF

CM GEN

G1=250,42

G2=4,8,16,32

VDD

LMP91051

CMOUT

+

-

PGA1

+

-

PGA2

A0

A1

CMOUT

IN1

SPI

GND

CSB

SCLK

SDIO

VIO

Optional

External

Filter

SPI

LMP91051

SNAS581B – MARCH 2012 – REVISED MAY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

BLOCK DIAGRAM

Configurable AFE for NDIR

TYPICAL APPLICATION

Typical NDIR Sensing Application Circuit

2

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