ADC3683 datasheet(12/91 Pages) TI2

12 / 91 page

6.8 Timing Requirements

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to

TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

ADC Timing Specifications

tAD

Aperture Delay

0.85

Aperture Jitter

Square wave clock with fast edges

180

Jitter on DCLKIN

± 50

tACQ

Signal acquisition period, referenced

to sampling clock falling edge

FS = 10 Msps

-TS/2

Sampling

Clock

Period

FS = 25 Msps

-TS/2

FS = 65 Msps

-TS/4

tCONV

Signal conversion period, referenced

to sampling clock falling edge

FS = 10 Msps

+TS ×

1/5

Sampling

Clock

Period

FS = 25 Msps

+TS ×

3/8

FS = 65 Msps

+TS ×

5/8

Wake up

time

Time to valid data after coming out of

power down. Internal reference.

Bandgap reference enabled, single ended clock

17.6

Bandgap reference enabled, differential clock

12.9

Bandgap reference disabled, single ended clock

2.2

Bandgap reference disabled, differential clock

2.2

Time to valid data after coming out of

power down.

External 1.6V reference.

Bandgap reference enabled, single ended clock

15.9

Bandgap reference enabled, differential clock

12.9

Bandgap reference disabled, single ended clock

1.7

Bandgap reference disabled, differential clock

1.7

tS,SYNC

Setup time for SYNC input signal

Referenced to sampling clock rising edge

500

tH,SYNC

Hold time for SYNC input signal

600

ADC

Latency

Signal input to data output

SLVDS 2-wire

ADC

clock

cycles

SLVDS 1-wire

SLVDS 1/2-wire

Add

Latency

Real decimation by 2

Output

clock

cycles

Complex decimation by 2

Real or complex decimation by 4, 8, 16, 32

ADC3681, ADC3682, ADC3683

SBAS872B – DECEMBER 2020 – REVISED OCTOBER 2022

www.ti.com

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