ADS1262IPWR datasheet(40/133 Pages) TI2

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9.3.7.2 PGA Absolute Output-Voltage Monitor

ADC1 contains an integrated a PGA absolute output-voltage monitor. If the absolute level of the PGA positive or

negative output exceeds VAVDD – 0.2 V, the PGA high alarm triggers (PGAH_ALM). If the absolute level of the

PGA positive or negative output voltage is less than VAVSS + 0.2 V, the PGA low alarm triggers (PGAL_ALM).

The alarms are set in the status byte corresponding to the conversion cycle when the alarms occurred. For

the next conversion cycle, the alarms reset. If the magnitude of PGA output voltages remains within the range

(VAVDD – 0.2 V and VAVSS + 0.2 V), the alarms remain reset. The PGA absolute output-voltage monitor block

diagram is shown in Figure 9-10.

VAVDD ± 0.2 V

VOUTP

VOUTN

PGA

ADC

Digital

Filter

VAVSS + 0.2 V

STATUS

DATA 1

DATA 2

DATA 3

DATA 4

PGAH_ALM

Bit 2 of STATUS byte

Latch

Supply Rail

Comparators

Data Bytes

CRC/CHK

Conversion

Start Reset

PGAL_ALM

Bit 3 of STATUS byte

Latch

Figure 9-10. PGA Absolute Output-Voltage Monitor

Figure 9-11 shows an example of the PGA absolute output-voltage monitor overrange event.

Conversions (DRDY)

VAVDD - 0.2

PGAH_ALM bit

Alarms latched during

conversion cycle

VAVSS + 0.2

PGAL_ALM bit

Figure 9-11. PGA Absolute Alarm

ADS1262, ADS1263

SBAS661C – FEBRUARY 2015 – REVISED MAY 2021

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