ADS1283IRHFR.B datasheet(21/67 Pages) TI2

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MFLAG

+100

(AINP

AINN)

-100

Time

MOD/2

MFLAG

100%FS

AINN

AINP

IABSI

ADS1283

www.ti.com

SBAS565C – JANUARY 2014 – REVISED AUGUST 2019

Product Folder Links: ADS1283

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If the inputs are sufficiently overdriven to drive the modulator to full duty cycle (that is, all 1s or all 0s), the

modulator enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on

the duration. A small-duration overdrive condition may not always clip the output code. When the input returns to

the normal range, the modulator requires up to 12 modulator clock cycles (fMOD) to exit saturation and return to

the linear region. The digital filter requires an additional 62 conversions for fully-settled data (linear-phase FIR).

In the extreme case of input overrange (where either overdriven input exceeds the voltage of the analog supply

voltage plus an internal ESD diode drop), the internal diodes begin to conduct, thus clipping the input signal.

When the input overdrive is removed, the diodes recover quickly. Make sure to limit the input current to 10 mA

(continuous duty) if an overvoltage condition is possible.

8.3.3.1.2

Modulator Input Impedance

The modulator samples the buffered input voltage with an internal capacitor to perform conversions. The

charging of the input sampling capacitor draws a transient current from the PGA output. Use the average value

of the current to calculate an effective input impedance, as shown in Equation 5:

REFF = 1 / (fMOD × CS)

where

•

fMOD = Modulator sample frequency = CLK / 4

•

CS = Input sampling capacitor = 17 pF (typ)

(5)

The resulting modulator input impedance is 55 k

Ω (CLK = 4.096 MHz). The modulator input impedance and the

internal PGA 300-Ω output resistors result in a systematic gain error of –1%. The modulator CS can vary ±20%

over production lots, affecting the nominal gain error.

8.3.3.1.3

Modulator Overrange Detection (MFLAG)

The ADS1283 has a fast-responding, overrange detection that indicates when the differential input exceeds

100% or –100% full-scale. The threshold tolerance is ±2.5%.The MFLAG output pin asserts high when in an

overrange condition. As Figure 32 and Figure 33 illustrate, the absolute differential input is compared to 100% of

range. The output of the comparator is sampled at the rate of fMOD / 2, yielding the MFLAG output. The minimum

detectable MFLAG pulse duration is fMOD / 2.

Figure 32. Modulator Overrange Block Diagram

Figure 33. Modulator Overrange Flag Operation

ADS1283IRHFR.B Datasheet(PDF) 21 Page - Texas Instruments

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