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ADS1283IRHFR.B Datasheet(PDF) 32 Page - Texas Instruments

Part # ADS1283IRHFR.B
Description  ADS1283 High-Resolution, Analog-to-Digital Converter
PDF  67 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS1283IRHFR.B Datasheet(HTML) 32 Page - Texas Instruments

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SYNC
DRDY
(Pulse-sync mode)
tCSDL
tSPWH
tDR
CLK
tSPWL
DRDY
(Continuous-sync mode)
DOUT
(Pulse-sync mode)
DOUT
(Continuous-sync mode)
New Data Ready
New Data Ready
32
ADS1283
SBAS565C – JANUARY 2014 – REVISED AUGUST 2019
www.ti.com
Product Folder Links: ADS1283
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Copyright © 2014–2019, Texas Instruments Incorporated
(1)
CLK rising edge to SYNC rising edge timing must not occur within the specified time window.
(2)
Continuous-sync mode; a free-running clock applied to the SYNC input without causing resynchronization. See Figure 46
8.4 Device Functional Modes
8.4.1 Synchronization (SYNC PIN and SYNC Command)
The ADS1283 can be synchronized to an external event, as well as to other ADS1283 devices if the
synchronization is applied simultaneously.
The ADS1283 has two sources for synchronization: the SYNC input pin and the SYNC command. The ADS1283
also has two synchronizing modes: pulse-sync and continuous-sync. In pulse-sync mode, the ADS1283
synchronizes to a single synchronization. In continuous-sync mode, either a single synchronization is used to
synchronize conversions, or a continuous clock is applied to the pin with a period equal to integer multiples of the
data rate. When the periods of the SYNC input and the DRDY output do not match, the ADS1283 resynchronizes
and conversions are restarted.
8.4.1.1 Pulse-Sync Mode
In pulse-sync mode, when a synchronization occurs (by pin or command), the ADS1283 unconditionally stops
and restarts the conversion process. When the ADC synchronizes, the device resets the internal filter memory,
DRDY goes high, and after the digital filter has settled, new conversion data are available as shown in Figure 45
and Table 12.
Figure 45. Pulse-Sync and Continuous-Sync Timing With Single Synchronization
Table 12. Pulse-Sync Timing for Figure 45 and Figure 46
PARAMETER
MIN
MAX
UNIT
tCSDL
CLK rising edge to SYNC rising edge(1)
30
–30
ns
tSYNC
SYNC clock period(2)
1
Infinite
n / fDATA
tSPWH, L
SYNC pulse width, high or low
2
1 / fCLK
tDR
Time for data ready (SINC filter)
See Table 13
Time for data ready (FIR filter)
62.98046875 / fDATA + 468 / fCLK



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