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ADS5500IPAP Datasheet(PDF) 27 Page - Texas Instruments

Part # ADS5500IPAP
Description  14-Bit, 125Msps ANALOG-TO-DIGITAL CONVERTER
PDF  37 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS5500IPAP Datasheet(HTML) 27 Page - Texas Instruments

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SERIAL PROGRAMMING INTERFACE
ADS5500
SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007
To use the input clock as the data capture clock, it is
Desired setup time = td– tSTART
necessary to delay the input clock by a delay (td) that
Desired hold time = tEND– td
results in the desired setup or hold time. Use either
of the following equations to calculate the value of td.
Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
tsu (ns)
th (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
FS (Msps)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
105
2.2
2.8
2.2
2.5
1.9
2.8
5.8
7.3
4.4
5.1
3.3
3.8
80
2.8
3.7
2.8
3.3
0.5
1.7
5.3
7.9
5.8
6.6
4.4
5.3
65
3.8
4.6
3.6
4.1
–0.5
0.8
5.3
8.5
6.7
7.2
5.5
6.4
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
tsu (ns)
th (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
FS (Msps)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
80
3.2
4.2
1.8
3
3.8
5
8.4
11
5.8
6.6
4.4
5.3
65
4.3
5.7
2
3
2.8
4.5
8.3
11.8
6.6
7.2
5.5
6.4
40
8.5
11
2.6
3.5
–1
1.5
8.9
14.5
7.5
8
7.3
7.8
20
17
25.7
2.5
4.7
–9.8
2
9.5
21.6
7.5
8
7.6
8
10
27
51
4
6.5
–30
–3
11.5
31
2
284
370
8
19
185
320
515
576
50
82
75
150
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
CLKOUT, Rise Time
CLKOUT, Fall Time
CLKOUT Jitter, Peak-to-Peak tJIT (ps)
Input-to-Output Clock Delay tPDI (ns)
tr (ns)
tf (ns)
FS (Msps)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
105
2
2.2
1.7
1.8
175
250
4
4.7
5.5
80
2.5
2.8
2.1
2.3
210
315
3.7
4.3
5.1
65
3.1
3.5
2.6
2.9
260
380
3.5
4.1
4.8
Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
CLKOUT, Rise Time
CLKOUT, Fall Time
CLKOUT Jitter, Peak-to-Peak tJIT (ps)
Input-to-Output Clock Delay tPDI (ns)
tr (ns)
tf (ns)
FS (Msps)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
80
2.5
2.8
2.1
2.3
210
315
7.1
8
8.9
65
3.1
3.5
2.6
2.9
260
380
7.8
8.5
9.4
40
4.8
5.3
4
4.4
445
650
9.5
10.4
11.4
20
8.3
9.5
7.6
8.2
800
1200
13
15.5
18
10
16
20.7
25.5
2
31
52
36
65
2610
4400
537
551
567
Note that some of these modes may modify the
standard operation of the device and possibly vary
the performance with respect to the typical data
The
ADS5500
has
internal
registers
for
the
shown in this data sheet.
programming of some of the modes described in the
previous sections. The registers should be reset after
Applying a RESET signal is required to set the
power-up by applying a 2
µs (minimum) high pulse
internal registers to their default states for normal
on RESET (pin 35); this also resets the entire ADC
operation. If the hardware RESET function is not
and sets the data outputs to low. This pin has a
used in the system, the RESET pin must be tied to
200-k
Ω internal pullup resistor to AV
DD.
The
ground and it is necessary to write the default values
programming is done through a three-wire interface.
to
the
internal
registers
through
the
serial
The timing diagram and serial register setting in the
programming interface. The registers must be written
Serial Programing Interface section describe the
in the following order.
programming of this register.
Write 9000h (Address 9, Data 000)
Table 2 shows the different modes and the bit values
Write A000h (Address A, Data 000)
to be written on the register to enable them.
Write B000h (Address B, Data 000)
Write C000h (Address C, Data 000)
27
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