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ADS7863ARGET Datasheet(PDF) 7 Page - Texas Instruments |
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ADS7863ARGET Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 42 page  BGND CHB1+ CHB1 - CHB0+ CHB0 - CHA1+ CHA1 - CHA0+ CHA0 - REF IN REF OUT AGND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BV DD SDOA SDOB BUSY CLOCK CS RD CONVST SDI M0 M1 AV DD CHA0 - REF IN REF OUT AGND AV DD M1 CHB1+ BGND BV DD SDOA SDOB BUSY 1 2 3 4 5 6 18 17 16 15 14 13 ADS7863A www.ti.com SBAS610 – DECEMBER 2013 PIN CONFIGURATIONS DBQ PACKAGE RGE PACKAGE SSOP-24 4-mm × 4-mm QFN-24 (Top View) (TOP VIEW) PIN DESCRIPTIONS PIN NUMBER NAME SSOP QFN DESCRIPTION AGND 12 4 Analog ground. Connect to analog ground plane. AVDD 13 5 Analog power supply, 2.7 V to 5.5 V. Decouple to AGND with a 1- μF ceramic capacitor. BGND 1 17 Buffer I/O ground. Connect to digital ground plane. ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the BUSY 21 13 conversion finishes. BVDD 24 16 Buffer I/O supply, 2.7 V to 5.5 V. Decouple to BGND with a 1- μF ceramic capacitor. CHA0– 9 1 Inverting analog input channel A0 CHA0+ 8 24 Noninverting analog input channel A0 CHA1– 7 23 Inverting analog input channel A1 CHA1+ 6 22 Noninverting analog input channel A1 CHB0– 5 21 Inverting analog input channel B0 CHB0+ 4 20 Noninverting analog input channel B0 CHB1– 3 19 Inverting analog input channel B1 CHB1+ 2 18 Noninverting analog input channel B1 CLOCK 20 12 External clock input Conversion start. The ADC switches from sample mode into hold mode on the CONVST rising edge, CONVST 17 9 independent of the CLOCK status. The conversion starts with the next CLOCK rising edge. CS 19 11 Chip select. When low, the SDOx outputs are active; when high, the SDOx outputs 3-state. M0 15 7 Mode pin 0. Selects between analog input channels (see Table 8). M1 14 6 Mode pin 1. Selects between the SDOx digital outputs (see Table 8). RD 18 10 Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low. REFIN 10 2 Reference voltage input. A 470-nF ceramic capacitor (min) is required at this terminal. REFOUT 11 3 Reference voltage output. The programmable internal voltage reference output is available on this pin. Serial data input. This pin allows the additional device features to be used but SDI can also be used in an SDI 16 8 ADS7861-compatible manner. Serial data output for converter A. When M1 is high, both SDOA and SDOB are active. Data are valid on SDOA 23 15 the falling CLOCK edge. SDOB 22 14 Serial data output for converter B. Data are valid on the falling CLOCK edge. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS7863A |
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