DAC80508 datasheet(21/59 Pages) TI2

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REF

OUT

CODE

GAIN

DIV

R-2R

DAC output

DAC

Buffer Register

LDAC Trigger

(synchronous mode)

DAC

Active Register

Serial Interface

DAC Data Register

WRITE

READ

(asynchronous mode)

VOUT

Gain

(x1 or x2)

GND

2.5 V

Reference

REF

REF Divider

(÷1 or ÷2)

DIV

GAIN

DAC80508, DAC70508, DAC60508

www.ti.com

SLASEL1D – JUNE 2017 – REVISED AUGUST 2018

Product Folder Links: DAC80508 DAC70508 DAC60508

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8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC) Architecture

Each output channel in the DACx0508 consists of an R-2R ladder architecture followed by an output buffer

amplifier. Figure 59 shows a block diagram of the DAC architecture.

Figure 59. DACx0508 DAC Block Diagram

8.3.1.1 DAC Transfer Function

The input data are written to the individual DAC Data registers in straight binary format. After a power-on or a

reset event, all DAC registers are set to either zero code (DACx0508Z) or midscale code (DACx0508M). The

DAC transfer function is given by Equation 1.

(1)

where:

CODE = decimal equivalent of the binary code that is loaded to the DAC register. CODE ranges from 0 to

2n – 1.

VREF = DAC reference voltage. Either VREFOUT from the internal 2.5 V reference or VREFIN if using an external

one.

n = resolution in bits. Either 12 (DAC60508), 14 (DAC70508) or 16 (DAC80508).

DIV = 1 or 2 as set by the REF-DIV bit in the GAIN register. Set to 1 by default.

GAIN = 1 or 2 as set by the BUFF-GAIN bit for that DAC channel in the GAIN register. Set to 1 by default in

DACx0508Z and to 2 in DACx0508M.

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