DRV8704DCPR datasheet(21/38 Pages) TI2

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DRV8704

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SLVSD29 – OCTOBER 2015

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7.5.1.4 BLANK Register (Address = 0x03h)

Table 7. BLANK Register

BIT

NAME

SIZE

R/W

DEFAULT

DESCRIPTION

7-0

TBLANK

R/W

0x80h

Sets current trip blanking time, in increments of 21

0x00h: 1.05 µs

…

0x32h: 1.05 µs

0x33h: 1.07 µs

…

0xFEh: 5.859 µs

0xFFh: 5.880 µs

Also sets minimum on-time of PWM

11-8

Reserved

—

Reserved

7.5.1.5 DECAY Register (Address = 0x04h)

Table 8. DECAY Register

BIT

NAME

SIZE

R/W

DEFAULT

DESCRIPTION

7-0

TDECAY

R/W

0x10h

Sets mixed decay transition time, in increments of

525ns

10-8

DECMOD

R/W

000

000: Force slow decay at all times

001: Reserved

010: Force fast decay at all times

011: Use mixed decay at all times

100: Reserved

101: Use auto mixed decay at all times

110 – 111: Reserved

Reserved

—

Reserved

7.5.1.6 Reserved Register Address = 0x05h

Table 9. Reserved Register

BIT

NAME

SIZE

R/W

DEFAULT

DESCRIPTION

11-0

Reserved

—

Reserved

7.5.1.7 DRIVE Register Address = 0x06h

Table 10. DRIVE Register

BIT

NAME

SIZE

R/W

DEFAULT

DESCRIPTION

1-0

OCPTH

R/W

OCP threshold

00: 250 mV

01: 500 mV

10: 750 mV

11: 1000 mV

3-2

OCPDEG

R/W

OCP deglitch time

00: 1.05 µs

01: 2.1 µs

10: 4.2 µs

11: 8.4 µs

5-4

TDRIVEN

R/W

Gate drive sink time

00: 263 ns

01: 525 ns

10: 1.05 µs

11: 2.10 µs

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