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DRV8704DCPR Datasheet(PDF) 8 Page - Texas Instruments |
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DRV8704DCPR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 38 page ![]() X X SCLK SDATI 1 3 4 2 SCS 5 6 7 8 SDATO SDATO valid 9 8 DRV8704 SLVSD29 – OCTOBER 2015 www.ti.com Product Folder Links: DRV8704 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated 6.6 SPI Timing Requirements over operating free-air temperature range (unless otherwise noted) NO. MIN MAX UNIT 1 tCYC Clock cycle time 250 ns 2 tCLKH Clock high time 25 ns 3 tCLCL Clock low time 25 ns 4 tSU(SDATI) Setup time, SDATI to SCLK 5 ns 5 tH(SDATI) Hold time, SDATI to SCLK 1 ns 6 tSU(SCS) Setup time, SCS to SCLK 5 ns 7 tH(SCS) Hold time, SCS to SCLK 1 ns 8 tL(SCS) Inactive time, SCS (between writes) 100 ns 9 tD(SDATO) Delay time, SCLK to SDATO (during read) 10 ns tSLEEP Wake time (SLEEPn inactive to high-side gate drive enabled) 1 ms tRESET Delay from power-up or RESETn high until serial interface functional 10 μs Figure 1. Timing Diagram |
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