150 W

V

T

=

1.25V

75 W

CDCLVD1213

Z = 50 W

LVPECL

100 nF

Z = 50 W

100 nF

75 W

150 W

350 W

V

T

=

1.25V

100 nF

CDCLVD1213

Z = 50 W

CML

Z = 50 W

100 nF

350 W

11

CDCLVD1213

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SCAS897A – JULY 2010 – REVISED OCTOBER 2016

Product Folder Links: CDCLVD1213

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Figure 13. CML Clock Driver Connected to CDCLVD1213 Input

Figure 14 illustrates how to connect an LVPECL input to the CDCLVD1213 input buffer. The input does not have

internal biasing, so external biasing (VCC/2 to VT) is required for AC coupling. The series resistors are required to

reduce the LVPECL signal swing if the signal swing is >1.6 Vpp.

Figure 14. LVPECL Clock Driver Connected to CDCLVD1213 Input