2.5 V

INP

INN

156.25 MHz LVDS

From Backplane

350

PHY

ASIC

V

T

DIV

2.5 V

1k

1k

FPGA

CPU

100

100

100

100

Copyright © 2016, Texas Instruments Incorporated

100

12

CDCLVD1213

SCAS897A – JULY 2010 – REVISED OCTOBER 2016

www.ti.com

Product Folder Links: CDCLVD1213

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Copyright © 2010–2016, Texas Instruments Incorporated

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVD1213 is a low additive jitter universal to LVDS fan-out buffer with an integrated frequency divider on

one output. The small package, low output skew, and low additive jitter make for a flexible device in demanding

applications.

9.2 Typical Application

Figure 15. Fan-Out Buffer for Line Card Application