VAC_REF

50 W

150 W

75 W

CDCLVD2102

Z = 50 W

LVPECL

100 nF

Z = 50 W

100 nF

75 W

150 W

50 W

V

IH +

V

IL

2

V

th =

CDCLVD2102

Z = 50 W

LVCMOS

(2.5V)

RS

CDCLVD2102

SCAS904A – MAY 2010 – REVISED JUNE 2010

www.ti.com

Figure 18 shows how to connect LVPECL inputs to the CDCLVD2102. The series resistors are required to

reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

Figure 18. LVPECL Clock Driver Connected to CDCLVD2102 Input

Figure 19 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2102 directly. The series

resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs

to be limited to VIH ≤ VCC.

Figure 19. 2.5V LVCMOS Clock Driver Connected to CDCLVD2102 Input

If one of the buffers is used, then the other unused buffer should be disabled through the EN pin, and the unused

input pins should be grounded by 1k

Ω resistors.

12

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