L9912 datasheet(51/84 Pages) STMICROELECTRONICS

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L9912

Watchdog

7.2

Watchdog error

A watch error occurs when the correct refresh word isn't sent in the correct time window; on

its occurrence the following behaviors are possible:



The Smart Power logic switches all the outputs off without resetting the microcontroller



The Smart Power logic switches all the outputs off and resets the microcontroller

On startup the system has 500 ms to configure or to disable the watchdog before an error.

The configuration is accomplished by writing the relevant SPI register.

On Power On reset the watchdog is configured to switch the outputs off leaving alive the

microcontroller whereas on Wakeup the watchdog keeps the configuration available before

entering the stand-by mode; this choice makes easier test and debug activities.

7.3

Watchdog freeze

The 500 ms watchdog startup window can be frozen by setting the INIT bit in the relevant

system initialization or to keep the watchdog frozen. In this condition it can be activated by

clearing the INIT bit.

7.4

Persistent watchdog failure

If, for any reason (HW or SW), the microcontroller is not in the condition to configure or to

freeze the watchdog unit the Smart Power logic will apply two sequences of 7 reset trials

before entering an idle state with the system definitively powered off. To eventually recover

the system, if possible, it is necessary to do a power on reset.

The picture shows the sequence: VDD is applied and NRES is released: after 7 consecutive

watchdog error occurrences VDD is released and a new 5 trials sequence is applied.

At the end of the sequence the Smart Power status depends on the key(s) status:



All keys off: the Smart Power enters the stand-by status



At least one key is on: the Smart Power remains alive with the power stages off

Figure 23. Persistent watchdog failure diagram

The watchdog reset count can be read and cleared through the relevant SPI register.

L9912 Datasheet(PDF) 51 Page - STMicroelectronics