L9924L datasheet(57/84 Pages) STMICROELECTRONICS

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L9924L

SPI interface

SPI interface is the communication channel between the microcontroller (Master) and the

Smart Power (Slave).

It consists of an input shift register, an output shift register and four control signals. MOSI

(Master Output Slave Input) is the data input line for the Smart Power input shift register.

MISO (Master Input Slave Output) is the data output line from the Smart Power output shift

12.1

SPI protocol

All SPI communications are executed in exact 24-bit increments. The EPONA contains a

data validation method through the SCK input to avoid transmission with a bit number not

equal to 24 bits from being written to the device. The SCK input counts the number of

received clocks and should the clock counter exceed or count fewer than 24 clocks, the

received message is discarded without changes to internal registers.

The general format of the 24-bit transmission frame for SPI interface is shown here below:

Data to the device (i.e. MOSI) consists of:

Data returned from the device (i.e. MISO) consists of:

The communications is controlled through CSN, enabling and disabling communication.

When CSN is at logic high, all SPI communication I/O is tri-stated and no data is accepted.

On the falling edge of CSN the data to be transmitted on MISO are latched and therefore the

Bit Position

23 22

21 20 19 18 17 16 15

13 12 11 10 9 8 7 6 5 4 3 2 1 0

GSW

RPAR

Data Bits

MISO

R/W

ADDR

RESERVED WPAR

Data Bits

MOSI

R/W Read/Write selection bit

ADDR [4-0] Register address bits

RESERVED -

WPAR Parity bit

DATA [13-0]

In write operation these bit are the data to be written to the destination register; in read

operation these bits define a key (0x0A5) to enable the read and clear feature of some

bits

GSW Global Status word

RPAR Parity bit

DATA [13-0] Data bit read from the addressed register

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