SPSB100 datasheet(194/213 Pages) STMICROELECTRONICS

194 / 213 page

PCB layout recommendation

In designing devices embedding high frequency switching converters, PCB layout is very important because it

affects noise pickup and can cause a good design to perform with results that are under the expectations.

Usually, the connections for the power components should be on the top layer with wide, copper-filled areas or

shapes. Moreover, it is desirable to make proper use of power planes and polygons for power distribution and

heat dissipation.

Output capacitors, inductors and the SPSB100 itself should be as close to each other as possible. This helps to

reduce the EMI radiated by the Powertraces due to the high switching currents through them and avoid inserting

any other additional components necessary to put in place a suitable filtering action.

Place the input capacitors directly at the VIN12 and VIN3 pins of SPSB100. The feedback parts of the system

should be kept away from the inductors and other noise sources.

The critical bypass components such as capacitors for VINx and VREG should be close to their respective pins. It

is important to place the feedback components including feedback resistors and compensation components close

to FBx and COMPx pins.

In a multilayer PCB, use at least one layer as a power ground plane, cause it is not always necessary to have a

dedicated signal ground plane. In any case, it is a good practice to have sensitive analog signals referenced to a

quiet ground location, to avoid any interferences with the high current loop. The QFN is a thermally enhanced

package. To effectively remove heat from the device the exposed pad should be connected to the ground plane

using via holes. Figures below illustrate the implementation of the layout guidelines outlined above, on the 4-layer

demo board.

As shown in the PCB layout:

•

Allow enough copper for VIN, GND and PHx

•

All bypass capacitors are placed as close as possible to their connecting pins

•

Components for loop compensation are placed as close as possible to the COMP pin

•

SGND as well as GND are connected to the inner PGND plane through via holes

•

PHx nodes copper should only be routed on the top layer to minimize switching noises

•

FBx trace routing is kept away from the software node

•

Thermal via holes are placed on VINx and PGND pads to improve thermal dissipation

Figure 72. Assembly top

SPSB100

PCB layout recommendation

DS14640 - Rev 2

page 194/213

SPSB100 Datasheet(PDF) 194 Page - STMicroelectronics