OPA4316IPW datasheet(6/65 Pages) TI2

6 / 65 page

OPA316, OPA2316, OPA2316S, OPA4316

SBOS703F – APRIL 2014 – REVISED OCTOBER 2016

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Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

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(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply

rails to 10 mA or less.

(3)

Short-circuit to ground, one amplifier per package.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage

Signal input pins

Voltage(2)

Common-mode

(V–) – 0.5

(V+) + 0.5

Differential

(V+) – (V–) + 0.2

Current(2)

–10

Output short-circuit(3)

Continuous

Operating temperature

–55

150

°C

Junction temperature

150

°C

Tstg

Storage temperature

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted).

VALUE

UNIT

V(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±4000

Charged device model (CDM), per JEDEC specification JESD22-C101(2)

±1500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).

MIN

MAX

UNIT

Supply voltage

1.8

5.5

Specified temperature

–40

125

°C

(1)

For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

6.4 Thermal Information: OPA316

THERMAL METRIC(1)

OPA316

UNIT

DBV (SOT23)

DCK (SC70)

5 PINS

RθJA

Junction-to-ambient thermal resistance(2)

221.7

263.3

°C/W

RθJC(top)

Junction-to-case(top) thermal resistance(3)

144.7

75.5

°C/W

RθJB

Junction-to-board thermal resistance(4)

49.7

°C/W

ψJT

Junction-to-top characterization parameter(5)

26.1

°C/W

ψJB

Junction-to-board characterization parameter(6)

50.3

°C/W

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