HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

S-1155 Series

Seiko Instruments Inc.

10

Standard Circuit

*1

*2

Input

Output

GND

Single GND

VOUT

VIN

VSS

ON/OFF

*2. Ceramic capacitor of 4.7

Figure 9

Caution

The above connection diagram and constant will not guarantee successful operation. Perform

thorough evaluation using the actual application to set the constant.

Application Conditions

4.7

µF or more

4.7

µF or more (ceramic capacitor)

Caution

2. Generally, series regulator may oscillate depending on the external components. Confirm that

no oscillation occurs in the application for which the above capacitors are used.

The S-1155 Series requires an output capacitor between the VOUT and VSS pin for phase compensation. Operation

is stabilized by a ceramic capacitor with an output capacitance of 4.7

µF or more over the entire temperature range.

When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be 4.7

µF or more.

The values of output overshoot and undershoot, which are transient response characteristics, vary depending on the

value of output capacitor.

The required value of capacitance for the input capacitor differs depending on the application.

≥ 4.7 µF

≥ 4.7 µF

Define the values by sufficient evaluation including the temperature characteristics under the usage

condition.