PCM186X datasheet(39/145 Pages) TI2

39 / 145 page

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SLAS831D – MARCH 2014 – REVISED MARCH 2018

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9.3.9.4.3

Clocking Configuration and Selection for Software-Controlled Devices

9.3.9.4.3.1

Target Clock Rates for ADC, DSP1 and DSP2

The ADC, DSP1 and DSP2 each have specific minimum clock requirements that can be driven from either the

incoming SCK or the output of the PLL, as shown in Table 8.

Table 8. Minimum Required Clock Ratios for ADC, DSP1 and DSP2

CORE

2-CHANNEL DEVICE RATIO

4-CHANNEL DEVICE RATIO

ADC

128x output sampling rate

DSP #1

256x output sampling rate

512x output sampling rate

DSP #2

256x output sampling rate

9.3.9.4.3.2

Configuration of Master Mode

If an external, high-quality MCLK is available (either on the SCK pin or XTAL), then configure the PCM186x to

run in master mode where possible, with the ADC and serial ports being driven from the MCLK or SCK source.

The on-chip DSPs may continue to require clocks from the PLL, as they run from a much higher clock rate.

Clock MUXs and overall configuration can be done in register Page0, 0x20. For the best performance in master

mode, the automatic clock configuration circuitry configures the clocks as shown in Table 9 and Table 10, if the

device is a PCM186x 2-channel or 4-channel, software-controlled device. The tables below show data at 48 kHz

multiples, the ratios for multiples of 44.1 kHz are identical, while the absolute MHz values will be multiples of 44.1

kHz instead of 48 kHz.

This automatic configuration can be bypassed using registers, starting from CLKDET_EN (Page.0, 0x20).

PCM186X Datasheet(PDF) 39 Page - Texas Instruments