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PCM5121PW Datasheet(PDF) 56 Page - Texas Instruments |
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PCM5121PW Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 121 page  t BUF t S-HD t LOW t D-SU t D-HD t SCL-F t SCL-R t RS-HD t RS-SU t SP t P-SU SDA SCL t HI START Repeated START STOP t SDA-R t SDA-F 56 PCM5121, PCM5122 SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018 www.ti.com Product Folder Links: PCM5121 PCM5122 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated Table 40. Write Operation - Basic I2C Framework Transmitter M M M S M S M S S M Data Type St slave address R/ ACK DATA ACK DATA ACK ACK Sp Table 41. Read Operation - Basic I2C Framework Transmitter M M M S S M S M M M Data Type St slave address R/ ACK DATA ACK DATA ACK NACK Sp M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition 8.4.1.1.2.4 Write Register A master can write to any PCM512x registers using single or multiple accesses. The master sends a PCM512x slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the data is received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 42 shows the write operation. Table 42. Write Operation Transmitter M M M S M S M S M S S M Data Type St slave addr W ACK inc reg addr ACK write data 1 ACK write data 2 ACK ACK Sp M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition; W = Write; ACK = Acknowledge 8.4.1.1.2.5 Read Register A master can read the PCM512x register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM512x slave address with a read bit after storing the register address. Then the PCM512x transfers the data which the index register points to. When auto-increment is enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 43 shows the read operation. Table 43. Read Operation Transmitter M M M S M S M M M S S M M M Data Type St slave addr W ACK inc reg addr ACK Sr slave addr R ACK data ACK NACK Sp M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated Start Condition; Sp = Stop Condition; W = Write; R = Read; NACK = Not acknowledge 8.4.1.1.2.6 Timing Characteristics Figure 74. Register Access Timing |
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