G2B

G2A

G1

C

B

A

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Data

Outputs

Select

Inputs

Enable

Inputs

1

2

3

6

4

5

15

14

13

12

11

10

9

7

Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.

Copyright © 2016, Texas Instruments Incorporated

10

SN54LVC138A, SN74LVC138A

SCAS291W – MARCH 1993 – REVISED OCTOBER 2016

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Product Folder Links: SN54LVC138A SN74LVC138A

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Copyright © 1993–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The SNx4LVC138A devices are 3-to-8 decoders and demultiplexers. The three input pins, A, B, and C, select

which output is active. The selected output is pulled LOW, while the remaining outputs are all HIGH. The

conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low

and one active-high enable inputs reduce the requirement for external gates or inverters when expanding. A 24-

line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An

enable input can be used as a data input for demultiplexing applications.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two

active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when

expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only

one inverter. An enable input can be used as a data input for demultiplexing applications.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 3-Line to 8-Line Decoder

This device features three binary inputs to select a single active-low output. Three enable pins are also available

to enable or disable the outputs. One active high enable and two active low enable pins are available, and any

enable pin can be deactivated to force all outputs high. All three enable pins must be active for the output to be

enabled.