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ICS8535BGI-01 REV. A NOVEMBER 9, 2007

ICS8535BI-01

LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER

PRELIMINARY

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

Ω

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal dis-

tortion. Figures 2A and 2B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts

may exist and it would be recommended that the board design-

ers simulate to guarantee compatibility across all printed circuit

and clock component process variations.

For applications not requiring the use of a clock input, it can be

left floating. Though not required, but for additional protection, a

1k

Ω resistor can be tied from the CLK input to ground.

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.