LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-

3.3V LVPECL FANOUT BUFFER

ICS8535BI-01

1

ICS8535BGI-01 REV. A NOVEMBER 9, 2007

PRELIMINARY

The ICS8535BI-01 is a low skew, high performance

1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout

buffer and a member of the HiPerClockS™ family

of High Performance Clock Solutions from IDT. The

ICS8535BI-01 has two single ended clock inputs.

the single ended clock input accepts LVCMOS or LVTTL input

levels and translate them to 3.3V LVPECL levels. The clock

enable is internally synchronized to eliminate runt clock pulses

on the output during asynchronous assertion/deassertion of

the clock enable pin.

Guaranteed output and part-to-part skew characteristics make

the ICS8535BI-01 ideal for those applications demanding well

defined performance and repeatability.

• Four differential 3.3V LVPECL outputs

• Selectable CLK0 or CLK1 inputs for redundant

and multiple frequency fanout applications

• CLK0 or CLK1 can accept the following input levels: LVCMOS

or LVTTL

• Maximum output frequency: 266MHz

• Translates LVCMOS and LVTTL levels to

3.3V LVPECL levels

• Output skew: TBD

• Part-to-part skew: TBD

• Propagation delay: 1.3ns (typical)

• Additive phase jitter, RMS: 0.04ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

HiPerClockS™

ICS

ICS8535BI-01

20-Lead TSSOP

4.4mm x 6.5mm x 0.925mm body package

G Package

Top View

nQ1

Q1

nQ0

Q0

CLK_EN

CLK_SEL

nc

CLK0

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Q2

nQ2

nc

Q3

nQ3

nc

nc

CLK1

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization

and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

ICS8535BI-01

20-Lead VFQFN

4mm x 4mm x 0.925mm body package

K Package

Top View

nQ3

Q3

CLK_EN

Q2

nQ2

nc

1

2

3

4

5

20 19 18 17 16

6

7

8

9

10

15

14

13

12

11

CLK0

CLK1

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

0

1

CLK_EN

CLK_SEL

D

Q

LE