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TLC5948APWPR Datasheet(PDF) 21 Page - Texas Instruments |
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TLC5948APWPR Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 54 page  TLC5948A www.ti.com SBVS192A – MARCH 2012 – REVISED DECEMBER 2012 Table 5 summarizes the GS data values versus the output on-time duty cycle. When the device powers up, the BLANK bit in the first control data latch is set to '1'. The 257-bit common shift register and the first and second GS data latches contain random data. Therefore, GS data must be written to the GS latches before the BLANK bit is set to '0'. All constant-current outputs are off when the BLANK bit is '1'. Table 5. Output Duty Cycle and On-Time versus GS Data GS DATA GS DATA DECIMAL HEX ON-TIME DUTY (%) DECIMAL HEX ON-TIME DUTY (%) 0 0 0 32768 8000 50.001 1 1 0.002 32769 8001 50.002 2 2 0.003 32770 8002 50.004 3 3 0.005 32771 8003 50.005 — — — — — — 8191 1FFF 12.499 40959 9FFF 62.499 8192 2000 12.500 40960 A000 62.501 8193 2001 12.502 40961 A001 62.502 — — — — — — 16381 3FFD 24.996 49149 BFFD 74.997 16382 3FFE 24.997 49150 BFFE 74.998 16383 3FFF 24.999 49151 BFFF 75.000 16384 4000 25.000 49152 C000 75.001 16385 4001 25.002 49153 C001 75.003 16386 4002 25.003 49154 C002 75.004 16387 4003 25.005 49155 C003 75.006 — — — — — — 24575 5FFF 37.499 57343 DFFF 87.500 24576 6000 37.501 57344 E000 87.501 24577 6001 37.502 57345 E001 87.503 — — — — — — 32765 7FFD 49.996 65533 FFFD 99.997 32766 7FFE 49.998 65534 FFFE 99.998 32767 7FFF 49.999 65535 FFFF 100.000 Conventional PWM Control In this PWM control, the GS clock is enabled when the BLANK bit is set to '0'. The first GS clock rising edge after the BLANK bit is set to '0' increments the GS counter by one and switches on all outputs with a non-zero GS value programmed into the second GS data latch. Each additional GS clock rising edge increases the corresponding GS counter by one. The GS counter keeps track of the number of clock pulses from the GS clock inputs. Each output stays on while the counter is less than or equal to the programmed GS value. Each output turns off at the GS counter value rising edge when the counter becomes greater than the output GS latch value. Figure 25 illustrates the conventional PWM operation. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TLC5948A |
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